SH7203 Datasheet, PDF (1676/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Interrupt priority level ............................ 131
Interrupt response time ........................... 174
Interrupt transfers ................................. 1210
IRQ interrupts ......................................... 157
Isochronous transfers ............................ 1211
J
Jump table base register (TBR) ................ 43
L
LCD controller (LCDC) ....................... 1225
LCD module power-supply states ........ 1277
LCDC timing ........................................ 1590
Load-store architecture ............................. 48
Local acceptance filter mask (LAFM).... 922
Logic operation instructions ..................... 74
Low-frequency mode.............................. 344
Low-power SDRAM .............................. 349
LRU ........................................................ 213
M
Mailbox........................................... 909, 913
Mailbox configuration ............................ 921
Mailbox control ...................................... 909
Manual reset ........................................... 126
Master receive operation......................... 847
Master transmit operation ....................... 845
Memory-mapped cache .......................... 226
Message control field.............................. 918
Message data fields................................. 923
Message receive sequence .................... 1001
Message transmission request......... 987, 996
Micro processor interface (MPI) ............ 909
Module standby function ...................... 1427
Module standby mode setting ................. 823
MPX-I/O interface.................................. 304
MTU2 functions ..................................... 442
MTU2 interrupts ..................................... 591
MTU2 output pin initialization............... 622
MTU2 timing........................................ 1568
Rev. 2.00 Apr. 16, 2008 Page 1646 of 1652
REJ09B0313-0200
Multi mode............................................ 1023
Multi-function timer pulse unit 2
(MTU2)................................................... 441
Multiplexed pins (port A) ..................... 1293
Multiplexed pins (port B)...................... 1293
Multiplexed pins (port C)...................... 1294
Multiplexed pins (port D) ..................... 1295
Multiplexed pins (port E)...................... 1296
Multiplexed pins (port F) ...................... 1298
Multiply and accumulate register high
(MACH).................................................... 44
Multiply and accumulate register low
(MACL) .................................................... 44
Multiply/Multiply-and-accumulate
operations.................................................. 49
N
NMI interrupt.......................................... 157
Noise filter .............................................. 857
Non-compressed modes .......................... 885
Nonlinearity error ................................. 1032
Non-numbers (NaN) ................................. 91
Normal space interface ........................... 296
Note on using a PLL oscillation circuit... 114
Notes on display-off mode
(LCDC stopped).................................... 1278
NRDY interrupt .................................... 1173
NYET handshake responses ................. 1209
O
Offset error............................................ 1032
On-chip peripheral module
interrupts ................................................. 159
On-chip peripheral module request......... 418
Operation for hardware rotation............ 1278
Operation in asynchronous mode............ 758
Operation in clocked synchronous
mode ....................................................... 769
Output load circuit ................................ 1595