SH7203 Datasheet, PDF (1256/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
Figure 24.1 shows a block diagram of LCDC.
LCD_CLK
Bck
Pck
Peripheral
bus
Clock
generator
DOTCLK
Register
LCDC
Pallet RAM
4 bytes × 256 entries
Bus interface
Power control
Line buffer
2.4 kbytes
BSC
External memory (VRAM)
Figure 24.1 LCDC Block Diagram
LCD_CL1
LCD_CL2
LCD_FLM
LCD_DATA 15 to 0
LCD_DON
LCD_VCPWC
LCD_VEPWC
LCD_M_DISP
Rev. 2.00 Apr. 16, 2008 Page 1226 of 1652
REJ09B0313-0200