SH7203 Datasheet, PDF (1126/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
FSRPC
0
R/W Full-Speed Receiver Operation Enable
Enables full-speed receiver operation.
0: Full-speed receiver operation is controlled by
hardware.
1: Full-speed receiver operation is enabled by
software.
1
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
USBE
0
R/W USB Block Operation Enable
Enables a software reset for this module. When
USBE is cleared to 0, the registers to be initialized by
a software reset is reset to the initial values. When
USBE = 0 is being set, the registers or bits to be
initialized by a software reset cannot be written. After
a software reset is executed, this bit should be set to
1 to enable this module operation.
0: USB block operation is disabled (software reset)
1: USB block operation is enabled
Rev. 2.00 Apr. 16, 2008 Page 1096 of 1652
REJ09B0313-0200