SH7203 Datasheet, PDF (1441/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
28.2.12 Deep Standby Cancel Source Select Register (DSSSR)
DSSSR is a 16-bit readable/writable register that consists of the bits for selecting the interrupt to
cancel deep standby mode. For IRQ0 to IRQ7, the settings are only valid if the pin functions are
assigned to PE4 to PE11. Only word access is valid.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit: 15 14 13 12 11 10
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R
9
8
7
6
5
4
3
2
1
0
- MRES IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 9 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
8
MRES
0
R/W Cancellation of Deep Standby Mode by Manual Reset
0: Deep standby mode is not canceled by a manual
reset.
1: Deep standby mode is canceled by a manual reset.
7
IRQ7
0
R/W Cancellation of Deep Standby Mode by IRQ7 (PE11)
0: Deep standby mode is not canceled by the IRQ7
interrupt.
1: Deep standby mode is canceled by the IRQ7
interrupt.
6
IRQ6
0
R/W Cancellation of Deep Standby Mode by IRQ6 (PE10)
0: Deep standby mode is not canceled by the IRQ6
interrupt.
1: Deep standby mode is canceled by the IRQ6
interrupt.
5
IRQ5
0
R/W Cancellation of Deep Standby Mode by IRQ5 (PE9)
0: Deep standby mode is not canceled by the IRQ5
interrupt.
1: Deep standby mode is canceled by the IRQ5
interrupt.
Rev. 2.00 Apr. 16, 2008 Page 1411 of 1652
REJ09B0313-0200