SH7203 Datasheet, PDF (1155/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.3.15 BEMP Interrupt Enabled Register (BEMPENB)
BEMPENB is a register that enables BEMP interrupts for each pipe.
This register is initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
PIPE7 PIPE6 PIPE5 PIPE4 PIPE3 PIPE2 PIPE1 PIPE0
BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE BEMPE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15 to 8 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
PIPE7BEMPE 0
R/W BEMP Interrupt Enable for PIPE7
0: Interrupt output disabled
1: Interrupt output enabled
6
PIPE6BEMPE 0
R/W BEMP Interrupt Enable for PIPE6
0: Interrupt output disabled
1: Interrupt output enabled
5
PIPE5BEMPE 0
R/W BEMP Interrupt Enable for PIPE5
0: Interrupt output disabled
1: Interrupt output enabled
4
PIPE4BEMPE 0
R/W BEMP Interrupt Enable for PIPE4
0: Interrupt output disabled
1: Interrupt output enabled
3
PIPE3BEMPE 0
R/W BEMP Interrupt Enable for PIPE3
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 2.00 Apr. 16, 2008 Page 1125 of 1652
REJ09B0313-0200