SH7203 Datasheet, PDF (1455/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
(3) Operation after Canceling Deep Standby Mode
After canceling deep standby mode, the LSI can be activated through the external bus or from the
on-chip RAM (for data retention), which can be selected by setting the RAMBOOT bit in
DSCTR2. By setting the CS0KEEPE bit, the states of the external bus control pins can be retained
even after cancellation of deep standby mode. Table 28.3 shows the pin states after cancellation of
deep standby mode according to the setting of each bit. Table 28.4 lists the external bus control
pins.
Table 28.3 Pin States after Cancellation of Deep Standby Mode and System Activation
Method by the DSCTR2 Settings
CS0KEEPE
Bit
0
0
1
1
RAMBOOT
Bit
0
1
0
1
Activation
Method
External bus
On-chip RAM
(for data
retention)
⎯
On-chip RAM
(for data
retention)
Pin States After Cancellation of Deep Standby
Mode
The states of the external bus control pins are not retained.
For other pins, the retention of their states is cancelled when
the IOKEEP bit is cleared.
The states of the external bus control pins are not retained.
After cancellation of deep standby mode, the retention of the
external bus control pin states is cancelled.
For other pins, the retention of their states is cancelled when
the IOKEEP bit is cleared.
Setting prohibited.
The states of the external bus control pin are retained.
The retention of the states of the external bus control pins
and other pins is cancelled when the IOKEEP bit is cleared.
Table 28.4 External Bus Control Pins in Different Modes
Operating Mode 0
(Activation through external 16-bit bus)
A[20:0]
D[15:0]
CS0, RD, CKIO
Operating Mode 1
(Activation through external 32-bit bus)
A[20:2]
D[31:0]
CS0, RD, CKIO
Rev. 2.00 Apr. 16, 2008 Page 1425 of 1652
REJ09B0313-0200