SH7203 Datasheet, PDF (1457/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
28.3.5 Module Standby Function
(1) Transition to Module Standby Function
Setting the standby control register MSTP bits to 1 halts the supply of clocks to the corresponding
on-chip peripheral modules. This function can be used to reduce the power consumption in the
program execution state and sleep mode. Disable a module before placing it in the module standby
mode. In addition, do not access the module's registers while it is in the module standby state.
For details on the states of registers, see section 30.3, Register States in Each Operating Mode.
(2) Canceling Module Standby Function
The module standby function can be canceled by clearing each MSTP bit to 0, or by a power-on
reset (only possible for RTC, H-UDI, UBC, and DMAC). When taking a module out of the
module standby state by clearing the corresponding MSTP bit to 0, read the MSTP bit to confirm
that it has been cleared to 0.
28.4 Usage Notes
28.4.1 Notes on Writing to Registers
When writing to the registers related to power-down modes, note the following.
When writing to the register related to power-down modes, the CPU, after executing a write
instruction, executes the next instruction without waiting for the write operation to complete.
Therefore, to reflect the change specified by writing to the register while the next instruction is
executed, insert a dummy read of the same register between the register write instruction and the
next instruction.
28.4.2 Notice about Deep Standby Control Register 2 (DSCTR2)
After (1) power-on reset by RES pin is released, and (2) the LSI transits to deep standby mode in
case that bit 7 (CS0KEEPE) and bit 6 (RAMBOOT) of deep standby control register 2 (DSCTR2)
are set to "1", these bits become unable to be written as "0" since then.
To write these as “0”, it is necessary to assert RES pin to low.
Rev. 2.00 Apr. 16, 2008 Page 1427 of 1652
REJ09B0313-0200