SH7203 Datasheet, PDF (929/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 Serial Sound Interface (SSI)
18.4.5 Receive Operation
Like transmission, reception can be controlled either by DMA or interrupt.
Figures 18.22 and 18.23 show the flow of operation.
When disabling the SSI module, the SSI clock* must be kept supplied until the IIRQ bit is in idle
state.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Oversampling clock when SCKD = 1.
Rev. 2.00 Apr. 16, 2008 Page 899 of 1652
REJ09B0313-0200