SH7203 Datasheet, PDF (148/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
Type
Exception Handling
Priority
Interrupt On-chip peripheral modules I²C bus interface 3 (IIC3)
High
Serial communications interface with FIFO
(SCIF)
Synchronous serial communications unit
(SSU)
Serial sound interface (SSI)
AND/NAND flash memory controller (FLCTL)
Realtime clock (RTC)
Controller area network (RCAN-TL1)
Instruction Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Slot illegal instructions (undefined code placed directly after a delayed
branch instruction*¹ (including FPU instructions and FPU-related CPU
instructions in FPU module standby state), instructions that rewrite the PC*²,
32-bit instructions*³, RESBANK instruction, DIVS instruction, and DIVU
instruction)
Low
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF.
2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N.
3. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B, MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S, MOVU.B, MOVU.W.
Rev. 2.00 Apr. 16, 2008 Page 118 of 1652
REJ09B0313-0200