SH7203 Datasheet, PDF (1207/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Powered
state
(DVSQ = 100)
Suspended
state
(DVSQ = 100)
USB bus reset detection
(when URST = 1, DVST is set to 1.)
Resume (RESM is set to 1)
USB bus reset detection
(when URST = 1, DVST is set to 1.)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Default
state
(DVSQ = 001)
Suspended
state
(DVSQ = 101)
Resume (RESM is set to 1)
SetAddress execution
(Address = 0)
(when URST = 1, DVST is set to 1.)
SetAddress execution
(when SADR = 1, DVST is set to 1.)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Address
state
(DVSQ = 010)
Suspended
state
(DVSQ = 110)
Resume (RESM is set to 1)
SetConfiguration
execution
(configuration value = 0)
(when SADR = 1,
DVST is set to 1.)
SetConfiguration execution
(configuration value = 0)
(when SCFG = 1, DVST is set to 1.)
Suspended state detection
(when SUSP = 1, DVST is set to 1.)
Configured
state
(DVSQ = 011)
Suspended
state
(DVSQ = 111)
Resume (RESM is set to 1)
Note: The URST, SADR, SCFG and SUSP bits in parentheses are enable bits that permit or block setting of the DVST bit to 1 by this module
when the corresponding stage transition is detected. (These enable bits are on INTENB0.)
Stage transitions are carried out even if setting the DVST bit to 1 is inhibited by these bits.
Figure 23.6 Device State Transitions
Rev. 2.00 Apr. 16, 2008 Page 1177 of 1652
REJ09B0313-0200