SH7203 Datasheet, PDF (1264/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 LCD Controller (LCDC)
24.3.3 LCDC Data Format Register (LDDFR)
LDDFR sets the bit alignment for pixel data in one byte and selects the data type and number of
colors used for display so as to match the display driver software specifications.
Bit: 15 14 13 12 11 10
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R
9
8
7
6
5
4
3
2
1
0
- PABD -
DSPCOLOR[6:0]
0
0
0
0
0
0
1
1
0
0
R R/W R R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 9 ⎯
8
PABD
7
⎯
Initial
Value R/W
All 0 R
0
R/W
0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Data Pixel Alignment
Sets the pixel data alignment type in one byte of data.
The contents of aligned data per pixel are the same
regardless of this bit's setting. For example, data H'05
should be expressed as B'0101 which is the normal
style handled by a MOV instruction of the this CPU, and
should not be selected between B'0101 and B'1010.
0: Big endian for byte data
1: Little endian for byte data
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1234 of 1652
REJ09B0313-0200