SH7203 Datasheet, PDF (1160/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
15
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
BCHG
0
R/W* USB Bus Change Interrupt Status
0: BCHG interrupts not generated
1: BCHG interrupts generated
13
SOFR
0
R/W* Frame Number Refresh Interrupt Status
0: SOF interrupts not generated
1: SOF interrupts generated
12
DTCH
0
R/W* Disconnection Detection Interrupt Status During Full-
Speed Operation
The disconnection detection using this bit is valid
only when the host controller function is selected and
full-speed operation is performed. During high-speed
operation, the disconnection detection, such as
detection of no response from a function, should be
executed using software.
0: DTCH interrupts not generated
1: DTCH interrupts generated
Note:
When high-speed operation established
(RHST = 11) is determined after a reset
handshake, keep DTCHE cleared to during
high-speed operation. Also, the DTCH bit
may be set to 1 during high-speed
communication. Therefore, do not fail to clear
DTCH to 0 after high-speed communication
completes.
11
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
BEMP
0
R/W Buffer Empty Interrupt Status
0: BEMP interrupts not generated
1: BEMP interrupts generated
9
NRDY
0
R
Buffer Not Ready Interrupt Status
0: NRDY interrupts not generated
1: NRDY interrupts generated
Rev. 2.00 Apr. 16, 2008 Page 1130 of 1652
REJ09B0313-0200