SH7203 Datasheet, PDF (1219/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.4.4 Buffer Memory
(1) Buffer Memory Allocation
Figure 23.9 shows an example of a buffer memory map for this module. The buffer memory is an
area shared by the CPU and this module. In the buffer memory status, there are times when the
access right to the buffer memory is allocated to the user system (CPU side), and times when it is
allocated to this module (SIE side).
The buffer memory sets independent areas for each pipe. In the memory areas, 64 bytes comprise
one block, and the memory areas are set using the first block number of the number of blocks
(specified using the BUFNMB and BUFSIZE bits in PIPEBUF). Moreover, three FIFO ports are
used for access to the buffer memory (reading and writing data). A pipe is assigned to the FIFO
port by specifying the pipe number using the CURPIPE bit in C/DnFIFOSEL.
The buffer statuses of the various pipes can be confirmed using the BSTS bit in DCPCTR and the
INBUFM bit in PIPEnCTR. Also, the access right of the FIFO port can be confirmed using the
FRDY bit in C/DnFIFOCTR.
Rev. 2.00 Apr. 16, 2008 Page 1189 of 1652
REJ09B0313-0200