SH7203 Datasheet, PDF (1429/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
28.2.5 Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. Only byte access is valid.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit:
Initial value:
R/W:
7
6
MSTP MSTP
57 56
1
1
R/W R/W
5
MSTP
55
1
R/W
4
MSTP
54
1
R/W
3
MSTP
53
1
R/W
2
MSTP
52
1
R/W
1
0
MSTP MSTP
51
50
1
1
R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP57 1
R/W Module Stop 57
When the MSTP57 bit is set to 1, the supply of the
clock to the IIC3-0 is halted.
0: IIC3-0 runs.
1: Clock supply to IIC3-0 is halted.
6
MSTP56 1
R/W Module Stop 56
When the MSTP56 bit is set to 1, the supply of the
clock to the IIC3-1 is halted.
0: IIC3-1 runs.
1: Clock supply to IIC3-1 is halted.
5
MSTP55 1
R/W Module Stop 55
When the MSTP55 bit is set to 1, the supply of the
clock to the IIC3-2 is halted.
0: IIC3-2 runs.
1: Clock supply to IIC3-2 is halted.
4
MSTP54 1
R/W Module Stop 54
When the MSTP54 bit is set to 1, the supply of the
clock to the IIC3-3 is halted.
0: IIC3-3 runs.
1: Clock supply to IIC3-3 is halted.
Rev. 2.00 Apr. 16, 2008 Page 1399 of 1652
REJ09B0313-0200