SH7203 Datasheet, PDF (1130/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
8
WKUP
0
R/W Wakeup Output
This bit is used to control remote wakeup signal
output to the USB bus. The module controls the
output time of a remote wakeup signal. When this bit
is set to 1, this module clears this bit to 0 after
outputting the 10-ms K state.
According to the USB specification, the USB bus idle
state must be kept for 5 ms or longer before a
remote wakeup signal is output. If this module writes
1 to this bit right after detection of suspended state,
the K state will be output after 2 ms.
0: Outputs no signals
1: Outputs a remote wakeup signal
Note: Do not write 1 to this bit, unless the device
state is in the suspended state (the DVSQ bit in
the INTSTS0 register is set to 1xx) and the
USB host enables the remote wakeup signal.
When this bit is set to 1, the USBCLK must not
be stopped even in the suspended state.
7
RWUPE
0
R/W Wakeup Detection Enable
Outputs a resume signal to a down port when a
remote wakeup signal is detected, by setting this bit
to 1. At this time, this module sets the RESUME bit
to 1.
0: Down-port wakeup is disabled.
1: Down-port wakeup is enabled.
Note: In setting this bit to 1, do not stop the USBCLK
even in the suspended state.
6
USBRST
0
R/W Bus Reset Output
Outputs a USB bus reset signal by setting this bit to
1. The USB bus reset signal output time should be
controlled by software. This bit should be cleared to
0 after the USB bus reset time has elapsed.
0: USB bus reset signal output is stopped.
1: USB bus reset signal is output.
Rev. 2.00 Apr. 16, 2008 Page 1100 of 1652
REJ09B0313-0200