SH7203 Datasheet, PDF (832/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Synchronous Serial Communication Unit (SSU)
(1) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 1, TE = 1, and RE = 1
SSCK
(2) When SSUMS = 0, BIDE = 0 (standard mode),
MSS = 0, TE = 1, and RE = 1
SSCK
Shift register
(SSTRSR)
SSO
SSI
Shift register
(SSTRSR)
SSO
SSI
(3) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 1, and either TE or RE = 1
SSCK
(4) When SSUMS = 0, BIDE = 1 (bidirectional mode),
MSS = 0, and either TE or RE = 1
SSCK
Shift register
(SSTRSR)
(5) When SSUMS = 1 and MSS = 1
Shift register
(SSTRSR)
SSO
SSI
SSCK
SSO
SSI
Shift register
(SSTRSR)
(6) When SSUMS = 1 and MSS = 0
Shift register
(SSTRSR)
SSO
SSI
SSCK
SSO
SSI
Figure 16.3 Relationship between Data Input/Output Pins and the Shift Register
Rev. 2.00 Apr. 16, 2008 Page 802 of 1652
REJ09B0313-0200