SH7203 Datasheet, PDF (1650/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions for this Edition
Item
16.4.2 Relationship of
Clock Phase, Polarity,
and Data
Page
800
16.4.4 Communication 804
Modes and Pin
Functions
Table 16.6
Communication Modes
and Pin States of SSCK
Pin
Table 16.7
Communication Modes
and Pin States of SCS
Pin
Revision (See Manual for Details)
Description added
… When SSUMS = 1, the CPHS setting is invalid although the
CPOS setting is valid. When SSUMS = 1, the transmit data
change timing and receive data fetch timing are the same as
that shown as “(1) When CPHS = 0” in figure 16.2.
Legend deleted
Table amended
Communication
Mode
SSUMS
SSU communication 0
mode
Register Setting
MSS
CSS1
0
x
1
0
0
CSS0
x
0
1
Pin State
SCS
Input
(Setting prohibited)
(Setting prohibited)
Rev. 2.00 Apr. 16, 2008 Page 1620 of 1652
REJ09B0313-0200