SH7203 Datasheet, PDF (628/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(4) Timing for Counter Clearing by Compare Match/Input Capture
Figure 11.84 shows the timing when counter clearing on compare match is specified, and figure
11.85 shows the timing when counter clearing on input capture is specified.
Pφ
Compare
match signal
Counter
clear signal
TCNT
N
H'0000
TGR
N
Figure 11.84 Counter Clear Timing (Compare Match)
Pφ
Input capture
signal
Counter clear
signal
TCNT
N
H'0000
TGR
N
Figure 11.85 Counter Clear Timing (Input Capture)
Rev. 2.00 Apr. 16, 2008 Page 598 of 1652
REJ09B0313-0200