SH7203 Datasheet, PDF (1423/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
28.2.1 Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of the power-down mode.
Only byte access is valid.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
STBY DEEP -
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W
7
STBY
0
R/W
6
DEEP
0
R/W
5 to 0 ⎯
All 0
R
[Legend]
x:
Don't care
Description
Software Standby, Deep Standby
Specifies transition to software standby mode or
deep standby mode.
0x: Executing SLEEP instruction puts chip into
sleep mode.
10: Executing SLEEP instruction puts chip into
software standby mode.
11: Executing SLEEP instruction puts chip into deep
standby mode.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1393 of 1652
REJ09B0313-0200