SH7203 Datasheet, PDF (922/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 Serial Sound Interface (SSI)
Figure 18.10 uses a system word length of 6 bits and a data word length of 4 bits. These settings
are not possible with the SSI module but are used only for clarification of the other configuration
bits.
• Inverted Clock
As basic sample format configuration except SCKP = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31
• Inverted Word Select
Figure 18.11 Inverted Clock
As basic sample format configuration except SWSP = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31 TD30 TD29 TD28 0 0 TD31
Figure 18.12 Inverted Word Select
• Inverted Padding Polarity
As basic sample format configuration except SPDP = 1
SSISCK
SSIWS
1st Channel
2nd Channel
SSIDATA TD28 1 1 TD31 TD30 TD29 TD28 1 1 TD31 TD30 TD29 TD28 1 1 TD31
Figure 18.13 Inverted Padding Polarity
Rev. 2.00 Apr. 16, 2008 Page 892 of 1652
REJ09B0313-0200