SH7203 Datasheet, PDF (244/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Cache
8.2 Register Descriptions
The cache has the following registers.
Table 8.2 Register Configuration
Register Name
Cache control register 1
Cache control register 2
Abbreviation R/W
CCR1
R/W
CCR2
R/W
Initial Value
H'00000000
H'00000000
Address
Access Size
H'FFFC1000 32
H'FFFC1004 32
8.2.1 Cache Control Register 1 (CCR1)
The instruction cache is enabled or disabled using the ICE bit. The ICF bit controls disabling of all
instruction cache entries. The operand cache is enabled or disabled using the OCE bit. The OCF
bit controls disabling of all operand cache entries. The WT bit selects either write-through mode
or write-back mode for operand cache.
Programs that change the contents of CCR1 should be placed in a cache-disabled space, and a
cache-enabled space should be accessed after reading the contents of CCR1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
ICF
-
-
ICE
-
-
-
-
OCF
-
WT OCE
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R
R R/W R
R
R
R R/W R R/W R/W
Rev. 2.00 Apr. 16, 2008 Page 214 of 1652
REJ09B0313-0200