SH7203 Datasheet, PDF (313/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Bit
10
9
8
7 to 5
Bit Name
RMODE
PDOWN
BACTV
⎯
Initial
Value
0
0
0
All 0
R/W Description
R/W Refresh Control
Specifies whether to perform auto-refresh or self-
refresh when the RFSH bit is 1. When the RFSH bit is
1 and this bit is 1, self-refresh starts immediately.
When the RFSH bit is 1 and this bit is 0, auto-refresh
starts according to the contents that are set in
registers RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
R/W Power-Down Mode
Specifies whether the SDRAM will enter the power-
down mode after the access to the SDRAM. With this
bit being set to 1, after the SDRAM is accessed, the
CKE signal is driven low and the SDRAM enters the
power-down mode.
0: The SDRAM does not enter the power-down mode
after being accessed.
1: The SDRAM enters the power-down mode after
being accessed.
R/W Bank Active Mode
Specifies to access whether in auto-precharge mode
(using READA and WRITA commands) or in bank
active mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT
commands)
Note:
Bank active mode can be used only when
either the upper or lower bits of the CS3 space
are used. When both the CS2 and CS3 spaces
are set to SDRAM, specify the auto-precharge
mode.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Apr. 16, 2008 Page 283 of 1652
REJ09B0313-0200