SH7203 Datasheet, PDF (621/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.5 Interrupt Sources
11.5.1 Interrupt Sources and Priorities
There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 6, Interrupt Controller (INTC).
Table 11.55 lists the MTU2 interrupt sources.
Table 11.55 MTU2 Interrupts
Channel Name Interrupt Source
Interrupt DMAC
Flag
Activation Priority
0
TGIA_0 TGRA_0 input capture/compare match TGFA_0 Possible
High
TGIB_0 TGRB_0 input capture/compare match TGFB_0 Not possible
TGIC_0 TGRC_0 input capture/compare match TGFC_0 Not possible
TGID_0 TGRD_0 input capture/compare match TGFD_0 Not possible
TCIV_0 TCNT_0 overflow
TCFV_0 Not possible
TGIE_0 TGRE_0 compare match
TGFE_0 Not possible
TGIF_0 TGRF_0 compare match
TGFF_0 Not possible
1
TGIA_1 TGRA_1 input capture/compare match TGFA_1 Possible
TGIB_1 TGRB_1 input capture/compare match TGFB_1 Not possible
TCIV_1 TCNT_1 overflow
TCFV_1 Not possible
TCIU_1 TCNT_1 underflow
TCFU_1 Not possible
2
TGIA_2 TGRA_2 input capture/compare match TGFA_2 Possible
TGIB_2 TGRB_2 input capture/compare match TGFB_2 Not possible
TCIV_2 TCNT_2 overflow
TCFV_2 Not possible
TCIU_2 TCNT_2 underflow
TCFU_2 Not possible Low
Rev. 2.00 Apr. 16, 2008 Page 591 of 1652
REJ09B0313-0200