SH7203 Datasheet, PDF (1147/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.3.11 Interrupts Enable Register 0 (INTENB0)
INTENB0 is a register that specifies the interrupt masks. The URST, SADR, SCFG and SUSP bits
operate as interrupt mask bits for the device state transition interrupt sources. The WDST, RDST,
CMPL and SERR bits operate as interrupt mask bits for the control transfer stage interrupt
sources.
This register is initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
VBSE RSME SOFE DVSE CTRE BEMPE NRDYE BRDYE URST SADR SCFG SUSP WDST RDST CMPL SERR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15
VBSE
0
R/W VBUS Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
14
RSME
0
R/W Resume Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
13
SOFE
0
R/W Frame Number Update Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
12
DVSE
0
R/W Device State Transition Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
11
CTRE
0
R/W Control Transfer Stage Transition Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
10
BEMPE
0
R/W Buffer Empty Interrupts Enable
0: Interrupt output disabled
1: Interrupt output enabled
Rev. 2.00 Apr. 16, 2008 Page 1117 of 1652
REJ09B0313-0200