SH7203 Datasheet, PDF (822/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W
Description
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, an SSTXI interrupt request
caused by transmit data empty is enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an SSRXI interrupt request
and an SSERI interrupt request caused by overrun error
are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, an SSERI interrupt request
caused by conflict error is enabled.
Rev. 2.00 Apr. 16, 2008 Page 792 of 1652
REJ09B0313-0200