SH7203 Datasheet, PDF (466/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Direct Memory Access Controller (DMAC)
CKIO
T1 T2 Taw T1 T2
Address
CS
RD
Data
WEn
DACKn
(Active low)
TEND
(Active low)
WAIT
Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit
is divided into multiple bus cycles and the CS is negated between
the bus cycles, TEND is also divided.
Figure 10.18 BSC Normal Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 2.00 Apr. 16, 2008 Page 436 of 1652
REJ09B0313-0200