SH7203 Datasheet, PDF (703/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Watchdog Timer (WDT)
13.3.3 Watchdog Reset Control/Status Register (WRCSR)
WRCSR is an 8-bit readable/writable register that controls output of the internal reset signal
generated by watchdog timer counter (WTCNT) overflow.
Note: The method for writing to WRCSR differs from that for other registers to prevent
erroneous writes. See section 13.3.4, Notes on Register Access, for details.
Bit: 7
6
5
4
3
2
1
0
WOVF RSTE RSTS -
-
-
-
-
Initial value: 0
0
0
1
1
1
1
1
R/W: R/(W) R/W R/W R
R
R
R
R
Bit
7
6
5
4 to 0
Bit Name
WOVF
RSTE
RSTS
⎯
Initial
Value
0
0
0
All 1
R/W
R/(W)
R/W
R/W
R
Description
Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in
watchdog timer mode. This bit is not set in interval
timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
[Clearing condition]
• When 0 is written to WOVF after reading WOVF
Reset Enable
Selects whether to generate a signal to reset the LSI
internally if WTCNT overflows in watchdog timer
mode. In interval timer mode, this setting is ignored.
0: Not reset when WTCNT overflows*
1: Reset when WTCNT overflows
Note: * LSI not reset internally, but WTCNT and
WTCSR reset within WDT.
Reset Select
Selects the type of reset when the WTCNT overflows
in watchdog timer mode. In interval timer mode, this
setting is ignored.
0: Power-on reset
1: Manual reset
Reserved
These bits are always read as 1. The write value
should always be 1.
Rev. 2.00 Apr. 16, 2008 Page 673 of 1652
REJ09B0313-0200