SH7203 Datasheet, PDF (1098/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
2
TEINTE 0
R/W Transfer End Interrupt Enable
Enables or disables an interrupt request to the CPU
when a transfer has been ended (TREND bit in
FLTRCR).
0: Disables the transfer end interrupt request to the
CPU
1: Enables the transfer end interrupt request to the CPU
1
TRINTE1 0
R/W FLECFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLECFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLECFIFO.
1: Enables an interrupt request to the CPU by a transfer
request from FLECFIFO.
When the DMA transfer is enabled, this bit should be
cleared to 0.
0
TRINTE0 0
R/W FLDTFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLDTFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLDTFIFO
1: Enables an interrupt request to the CPU by a transfer
request from FLDTFIFO
When the DMA transfer is enabled, this bit should be
cleared to 0.
Note: * Only 0 can be written to these bits.
Rev. 2.00 Apr. 16, 2008 Page 1068 of 1652
REJ09B0313-0200