SH7203 Datasheet, PDF (1149/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
2
RDST
0
R/W Control Read Stage Transition Notifications Enable
0: CTRT interrupt disabled at transition to control
read stage
1: CTRT interrupt enabled at transition to control
read stage
1
CMPL
0
R/W Control Transfer End Notifications Enable
0: CTRT interrupt disabled at detection of the end of
control transfer
1: CTRT interrupt enabled at detection of the end of
control transfer
0
SERR
0
R/W Control Transfer Sequence Error Notifications
Enable
0: CTRT interrupt disabled at detection of control
transfer sequence error
1: CTRT interrupt enabled at detection of control
transfer sequence error
Note: After the interrupt status was cleared, an interval of 80 ns or more is required before
enabling/disabling the corresponding interrupt.
Rev. 2.00 Apr. 16, 2008 Page 1119 of 1652
REJ09B0313-0200