SH7203 Datasheet, PDF (1670/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions for this Edition
Item
31.4.2 Control Signal
Timing
Table 31.7 Control
Signal Timing
Page
1528
Revision (See Manual for Details)
Table amended
Bφ = 66.66 MHz
Item
Symbol
Bus buffer off time 1
t
BOFF1
Bus buffer off time 2
t_BOFF2
Bus buffer on time 1
t_BON1
Bus buffer on time 2
t_BON2
BACK setup time when bus buffer off t
BACKS
Min.
—
—
—
—
0
Max.
15
15
15
15
—
Unit
ns
ns
ns
ns
ns
Figure 31.12 Bus
Release Timing
1530 Figure amended
BACK
A25 to A0,
D31 to D0
t_BACKD
t_BACKS
t_BOFF1
t_BOFF2
t_BACKD
t_BON1
t_BON2
31.4.3 Bus Timing
Table 31.8 Bus Timing
1531 to
1533
Table and notes amended
Item
Address delay time 1
Symbol
t_AD1
Bφ = 66.66 MHz*¹*²
Min.
Max.
1
13
Unit
ns
Chip enable setup time
t
0
—
ns
CS
CS delay time 1
t
1
13
ns
CSD1
Read write delay time 1
t_RWD1
1
13
ns
WAIT setup time
t_WTS
WAIT hold time
t
WTH
Address setup time relative to t_AWH
AH
DACK, TEND delay time
t_DACD
1/2t_cyc + 5.5 —
ns
1/2t + 4.5 —
ns
cyc
1/2t_cyc - 2 —
ns
Refer to DMAC timing ns
Figure
Figures 31.13 to
31.38, 31.40 to
31.44
Figures 31.13 to
31.16, 31.21
Figures 31.13 to
31.38, 31.41 to
31.44
Figures 31.13 to
31.38, 31.41 to
31.44
Figures 31.14 to
31.21, 31.42, 31.44
Figures 31.14 to
31.21, 31.42, 31.44
Figure 31.17
Figures 31.13 to
31.35, 31.39, 31.41
to 31.44
Notes: 1. The maximum value (fmax) of Bφ (external bus
clock) depends on the number of wait cycles and
the system configuration of your board.
2. 1/2 t_cyc indicated in minimum and maximum values
for the item of delay, setup, and hold times
represents a half cycle from the rising edge with a
clock. That is, 1/2 t_cyc describes a reference of the
falling edge with a clock.
Rev. 2.00 Apr. 16, 2008 Page 1640 of 1652
REJ09B0313-0200