SH7203 Datasheet, PDF (1179/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
Initial
Value R/W Description
6
SQMON
1
R
Toggle Bit Confirmation
0: DATA0
1: DATA1
When the function controller function is selected,
this module initializes this bit to 1 immediately after
the SETUP token of the control transfer has been
received.
5 to 3 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
CCPL
0
R/W Control Transfer End Enable
0: Invalid
1: The control transfer is ended
When the function controller function is selected,
this bit is cleared to 0 immediately after the SETUP
token has been received. When the host controller
function is selected, this bit should be cleared to 0.
1, 0
PID[1:0]
00
R/W Response PID
00: NAK response
01: BUF response (depending on the buffer state)
10: STALL response
11: STALL response
When the function controller function is selected,
these bits are cleared to B'00 immediately after the
SETUP token has been received. If a transfer error
is detected, the controller sets these bits to end the
transfer.
Notes: 1. This bit is valid only when 0 is read.
2. This bit is valid only when 1 is written to.
3. The SQCLR SQSET bits should not be set to 1 at the same time. Before operating
either bit, PID = NAK should be set.
4. To change the SQSET or SQCLR bit in this register and that in PIPEnCTR in
succession (to change the PID sequence toggle bits of multiple pipes in succession), an
access cycle of at least 120 ns and 5 or more bus clock cycles is required.
Rev. 2.00 Apr. 16, 2008 Page 1149 of 1652
REJ09B0313-0200