SH7203 Datasheet, PDF (1668/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Main Revisions for this Edition
Item
Page
29.2 Input/Output Pins 1430
Table 33.1 Pin
Configuration
29.5 Usage Notes
1436
30.1 Register
1445
Addresses (by functional
module, in order of the
corresponding section
numbers)
30.2 Register Bits
1480
1484
Revision (See Manual for Details)
Table amended
Pin Name
Symbol
Clock pin for H-UDI serial data TCK
I/O
I/O
Input
Function
Data is serially supplied to the H-UDI from
the data input pin (TDI), and output from
the data output pin (TDO), in
synchronization with this clock.
Description amended
4. When the TDO change timing switch command is set and
the TRST pin is asserted immediately after and the RES
pin is negated, the TDO change timing switch command
may be cleared. To prevent this, make sure to insert an
interval of 20 t_cyc or more between the signal changes of
the RES and TRST pins when the TDO change timing
switch command is set. Make sure to put 20 t or more
cyc
between the signal change timing of the RES and TRST
pins. For details, see 29.4.3, TDO Output Timing.
Table amended
Module
Name
MTU2
Register Name
Timer dead time enable register
Timer waveform control register
Timer output level buffer register
CMT
Compare match counter_0
Compare match constant
register_0
Compare match timer control/
status register_1
Compare match counter_1
Compare match constant
register_1
Abbreviation
TDER
TWCR
TOLBR
CMCNT0
CMCOR0
CMCSR1
CMCNT1
CMCOR1
Number
of Bits Address
8
H'FFFE4234
8
H'FFFE4260
8
H'FFFE4236
16
H'FFFEC004
16
H'FFFEC006
Access
Size
8
8
8
8, 16
8, 16
16
H'FFFEC008 16
16
H'FFFEC00A 8, 16
16
H'FFFEC00C 8, 16
Table amended
Module
Name
MTU2ã©·
ã©·
ã©·
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
TDERã©·
⎯㩷
⎯㩷
⎯㩷
⎯㩷
⎯㩷
⎯㩷
⎯㩷
TDER
TWCRã©·
CCEã©·
⎯㩷
⎯㩷
⎯㩷
⎯㩷
⎯㩷
⎯㩷
WRE
TOLBRã©·
⎯㩷
⎯㩷
OLS3Nã©·
OLS3Pã©·
OLS2Nã©·
OLS2Pã©·
OLS1Nã©·
OLS1P
Table amended
Module
Name
SSU
Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
SSCRL_0
⎯
SSUMS
SRES
⎯
⎯
⎯
DATS[1]
DATS[0]
SSCRL_1
⎯
SSUMS
SRES
⎯
⎯
⎯
DATS[1]
DATS[0]
Rev. 2.00 Apr. 16, 2008 Page 1638 of 1652
REJ09B0313-0200