SH7203 Datasheet, PDF (321/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
Table 9.6 16-Bit External Device Access and Data Alignment in Big Endian
Data Bus
Operation
D31 to D23 to D15 to
WE3,
D24 D16 D8
D7 to D0 DQMUU
Byte access at 0
⎯
⎯
Data
⎯
⎯
7 to 0
Byte access at 1
⎯
⎯
⎯
Data
⎯
7 to 0
Byte access at 2
⎯
⎯
Data
⎯
⎯
7 to 0
Byte access at 3
⎯
⎯
⎯
Data
⎯
7 to 0
Word access at 0
⎯
⎯
Data
Data
⎯
15 to 8 7 to 0
Word access at 2
⎯
⎯
Data
Data
⎯
15 to 8 7 to 0
Longword 1st
⎯
⎯
Data
Data
⎯
access at 0 time at 0
31 to 24 23 to 16
2nd
⎯
⎯
Data
Data
⎯
time at 2
15 to 8 7 to 0
Strobe Signals
WE2,
DQMUL
WE1,
DQMLU
⎯
Assert
⎯
⎯
⎯
Assert
⎯
⎯
⎯
Assert
⎯
Assert
⎯
Assert
⎯
Assert
WE0,
DQMLL
⎯
Assert
⎯
Assert
Assert
Assert
Assert
Assert
Rev. 2.00 Apr. 16, 2008 Page 291 of 1652
REJ09B0313-0200