SH7203 Datasheet, PDF (1142/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
12
DREQE
11, 10 MBW[1:0]
9
TRENB
8
TRCLR
Initial
Value R/W
0
R/W
0
R/W
0
R/W
0
R/W*¹
Description
DMA Transfer Request Enable
0: Request disabled
1: Request enabled
FIFO Port Access Bit Width
00: 8-bit width
01: 16-bit width
10: 32-bit width
11: Setting prohibited
When the selected CURPIPE is set to the buffer
memory read direction, set these bits and the
CURPIPE bits simultaneously.
For details, see 23.4.4, Buffer Memory.
Note: Once reading from the buffer memory is
started, the access bit width of the FIFO port
cannot be changed until all of the data has
been read. Also, the bit width cannot be
changed from the 8-bit width to the 16-/32-bit
width or from the 16-bit width to the 32-bit width
while data is being written to the buffer
memory.
Transaction Counter Enable
This bit is valid when the receiving direction (reading
from the buffer memory) has been set for the pipe
specified by the CURPIPE bits.
0: Transaction counter function is invalid.
1: Transaction counter function is valid.
Transaction Counter Clear
This bit is valid when the receiving direction (reading
from the buffer memory) has been set for the pipe
specified by the CURPIPE bits.
0: Invalid
1: The current count is cleared.
Rev. 2.00 Apr. 16, 2008 Page 1112 of 1652
REJ09B0313-0200