SH7203 Datasheet, PDF (1425/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
4
MSTP7
0
R/W Module Stop 7
When the MSTP7 bit is set to 1, the supply of the clock
to the FPU is halted. After setting the MSTP7 bit to 1,
the MSTP7 bit cannot be cleared by writing 0. This
means that, after the supply of the clock to the FPU is
halted by setting the MSTP7 bit to 1, the supply cannot
be restarted by clearing the MSTP7 bit to 0.
To restart the supply of the clock to the FPU after it was
halted, reset the LSI by a power-on reset.
0: FPU runs.
1: Clock supply to FPU is halted.
3 to 0 ⎯
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
28.2.3 Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. Only byte access is valid.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit: 7
HIZ
Initial value: 0
R/W: R/W
6
5
4
-
MSTP
35
-
1
1
1
R R/W R
3
2
1
0
-
MSTP MSTP MSTP
32
31
30
1
1
1
0
R R/W R/W R/W
Rev. 2.00 Apr. 16, 2008 Page 1395 of 1652
REJ09B0313-0200