SH7203 Datasheet, PDF (207/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc + m1
1 Icyc + m1 + 2(m2) + m3
IRQ
m1 m2 m3
m1 m2
F D E EMMM
First instruction in interrupt exception
service routine
FD
First instruction in multiple interrupt
exception service routine
D E EMMM
FD
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Interrupt acceptance Multiple interrupt acceptance
Figure 6.5 Example of Pipeline Operation for Multiple Interrupts
(No Register Banking)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in interrupt exception
service routine
F D E EMMME
FDE
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 6.6 Example of Pipeline Operation when IRQ Interrupt is Accepted
(Register Banking without Register Bank Overflow)
Rev. 2.00 Apr. 16, 2008 Page 177 of 1652
REJ09B0313-0200