SH7203 Datasheet, PDF (1195/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Bit
DVST
CTRT
BEMP
Section 23 USB 2.0 Host/Function Module (USB)
Interrupt Name Cause of Interrupt
Function That
Generates the Related
Interrupt
Status
Device state
transition
interrupt
When a device state transition is
detected
• A USB bus reset detected
Function
DVSQ
• The suspend state detected
• Set address request received
• Set configuration request received
Control transfer When a stage transition is detected in Function
stage transition control transfer
interrupt
• Setup stage completed
CTSQ
• Control write transfer status stage
transition
• Control read transfer status stage
transition
• Control transfer completed
• A control transfer sequence error
occurred
Buffer empty
interrupt
• When transmission of all of the
data in the buffer memory has
been completed
Host,
Function
BEMPSTS.
PIPEBEMP
• When an excessive maximum
packet size error has been
detected
Rev. 2.00 Apr. 16, 2008 Page 1165 of 1652
REJ09B0313-0200