SH7203 Datasheet, PDF (1675/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

DMAC timing....................................... 1567
DREQ pin sampling timing .................... 433
DTCH interrupt..................................... 1181
Dual address mode.................................. 425
E
ECC code.............................................. 1084
ECC error check ................................... 1084
Effective address calculation .................... 52
Electrical characteristics ....................... 1513
Endian..................................................... 289
Equation for getting SCBRR value......... 736
Example of time triggered system .......... 997
Exception handling ................................. 117
Exception handling state........................... 85
Exception handling vector table ............. 121
Exception source generation
immediately after delayed branch
instruction ............................................... 137
Exceptions triggered by instructions....... 133
External request mode ............................ 416
External trigger input timing................. 1030
F
Fixed mode ............................................. 421
FLCTL interrupt requests ..................... 1087
FLCTL timing....................................... 1580
Floating point operation instructions ...... 136
Floating-point exceptions ......................... 97
Floating-point format................................ 88
Floating-point operation instructions........ 79
Floating-point ranges ................................ 90
Floating-point registers ............................. 93
Floating-point unit (FPU) ......................... 87
Flow of the user break operation ............ 202
Format of double-precision
floating-point number ............................... 88
Format of single-precision
foating-point number ................................ 88
FPU exception handling ........................... 97
FPU exception sources.............................. 97
FPU-related CPU instructions................... 81
Frame update interrupt .......................... 1179
Full-scale error ...................................... 1032
G
General illegal instructions ..................... 135
General registers ....................................... 41
Global base register (GBR)....................... 43
H
Halt mode................................................ 983
H-UDI commands ................................. 1432
H-UDI interrupt ............................ 157, 1435
H-UDI reset........................................... 1435
H-UDI timing........................................ 1593
I
I/O port timing ...................................... 1592
I/O ports ................................................ 1357
I²C bus format ......................................... 844
I²C bus interface 3 (IIC3)........................ 825
ID reorder................................................ 931
IIC3 timing............................................ 1574
Immediate data.......................................... 50
Immediate data accessing.......................... 50
Immediate data format .............................. 47
Influences on absolute precision ........... 1036
Initial values of control registers............... 45
Initial values of general registers .............. 45
Initial values of system registers ............... 45
Instruction features.................................... 48
Instruction format...................................... 57
Instruction set............................................ 61
Integer division instructions.................... 135
Internal arbitration for transmission........ 987
Interrupt controller (INTC) ..................... 141
Interrupt exception handling ................... 132
Interrupt exception handling
vectors and priorities............................... 161
Rev. 2.00 Apr. 16, 2008 Page 1645 of 1652
REJ09B0313-0200