SH7203 Datasheet, PDF (440/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Direct Memory Access Controller (DMAC)
Table 10.3 Combinations of Priority Mode Bits
Transfer Priority
End
Mode Bits High
Priority Level at the End of Transfer
Low
Mode
CH No.
Mode 0
Any
(fixed mode 1) channel
Mode 1
Any
(fixed mode 2) channel
Mode 2
(round-robin
mode)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
PR[1] PR[0] 0
0
0
CH0
0
1
CH0
1
1
CH1
1
1
CH2
1
1
CH3
1
1
CH0
1
1
CH0
1
1
CH0
1
1
CH0
1
1
CH0
1
CH1
CH4
CH2
CH3
CH0
CH1
CH1
CH1
CH1
CH1
2
CH2
CH1
CH3
CH0
CH1
CH2
CH2
CH2
CH2
CH2
3
CH3
CH5
CH0
CH1
CH2
CH3
CH3
CH3
CH3
CH3
4
CH4
CH2
CH4
CH4
CH4
CH4
CH4
CH4
CH4
CH4
5
CH5
CH6
CH5
CH5
CH5
CH5
CH5
CH5
CH5
CH5
6
CH6
CH3
CH6
CH6
CH6
CH6
CH6
CH6
CH6
CH6
7
CH7
CH7
CH7
CH7
CH7
CH7
CH7
CH7
CH7
CH7
Rev. 2.00 Apr. 16, 2008 Page 410 of 1652
REJ09B0313-0200