SH7203 Datasheet, PDF (160/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
5.5 Interrupts
5.5.1 Interrupt Sources
Table 5.8 shows the sources that start interrupt exception handling. These are divided into NMI,
user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules.
Table 5.8 Interrupt Sources
Type
NMI
User break
H-UDI
IRQ
PINT
On-chip peripheral module
Request Source
NMI pin (external input)
User break controller (UBC)
User debugging interface (H-UDI)
IRQ0 to IRQ7 pins (external input)
PINT0 to PINT7 pins (external input)
Direct memory access controller (DMAC)
USB2.0 host/function module (USB)
LCD controller (LCDC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
Multi-function timer pulse unit 2 (MTU2)
A/D converter (ADC)
I²C bus interface 3 (IIC3)
Serial communications interface with FIFO (SCIF)
Synchronous serial communications unit (SSU)
Serial sound interface (SSI)
AND/NAND flash memory controller (FLCTL)
Realtime clock (RTC)
Controller area network (RCAN-TL1)
Number of
Sources
1
1
1
8
8
16
1
1
2
1
1
25
1
20
16
6
4
4
3
10
Each interrupt source is allocated a different vector number and vector table offset. See table 6.4
in section 6, Interrupt Controller (INTC), for more information on vector numbers and vector table
address offsets.
Rev. 2.00 Apr. 16, 2008 Page 130 of 1652
REJ09B0313-0200