SH7203 Datasheet, PDF (1424/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
28.2.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. Only byte access is valid.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP
10
9
8
7
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
R
Initial
Bit
Bit Name Value R/W Description
7
MSTP10 0
R/W Module Stop 10
When the MSTP10 bit is set to 1, the supply of the
clock to the H-UDI is halted.
0: H-UDI runs.
1: Clock supply to H-UDI halted.
6
MSTP9
0
R/W Module Stop 9
When the MSTP9 bit is set to 1, the supply of the clock
to the UBC is halted.
0: UBC runs.
1: Clock supply to UBC halted.
5
MSTP8
0
R/W Module Stop 8
When the MSTP8 bit is set to 1, the supply of the clock
to the DMAC is halted.
0: DMAC runs.
1: Clock supply to DMAC halted.
Rev. 2.00 Apr. 16, 2008 Page 1394 of 1652
REJ09B0313-0200