SH7203 Datasheet, PDF (1593/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 Electrical Characteristics
CKIO
A25 to A0
CExx
RD/WR
RD
Read
D15 to D0
Write
WE
D15 to D0
BS
DACKn
TENDn*
WAIT
Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm2w
t_AD1
t_AD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RSD
t_WDD1
t_WED1
t_BSD
t_BSD
t_DACD
t_RSD
t_RDS1
t_RDH1
t_WED1
t_WDH1
t_WTH
t_WTS
t_WTH
t_WTS
t_DACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 31.42 PCMCIA Memory Card Bus Cycle
(TED = 2 Cycles, TEH = 1 Cycle, Software Wait Cycle 0, Hardware Wait Cycle 1)
Rev. 2.00 Apr. 16, 2008 Page 1563 of 1652
REJ09B0313-0200