SH7203 Datasheet, PDF (386/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Bus State Controller (BSC)
CKIO
A25 to A0
CSn
WEn
T1
T2
RD/WR
Read
RD
D31 to D0
RD/WR
Write
RD
D31 to D0
High
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.37 Basic Access Timing for SRAM with Byte Selection (BAS = 1)
Rev. 2.00 Apr. 16, 2008 Page 356 of 1652
REJ09B0313-0200