SH7203 Datasheet, PDF (899/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Figure 18.2 shows a block diagram of the SSI module.
Section 18 Serial Sound Interface (SSI)
Serial audio bus
SSIDATA
Peripheral bus
SSI module
Control
circuit
Interrupt
request
Register
SSICR
SSISR
SSITDR
SSIRDR
DMA request
Data buffer
Barrel shifter
MSB
Shift register
LSB
SSIWS
Bit counter
SSISCK
Serial clock control
Divider
EXTAL
XTAL
CKIO
AUDIO_CLK
AUDIO_X1
AUDIO_X2
Legend:
SSICR: Control register
SSISR: Status register
SSITDR: Transmit data register
SSIRDR: Receive data register
Figure 18.2 Block Diagram of SSI
Rev. 2.00 Apr. 16, 2008 Page 869 of 1652
REJ09B0313-0200