SH7203 Datasheet, PDF (25/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

23.4.3 Pipe Control ........................................................................................................ 1182
23.4.4 Buffer Memory ................................................................................................... 1189
23.4.5 Control Transfers (DCP)..................................................................................... 1205
23.4.6 Bulk Transfers (PIPE1 to PIPE5)........................................................................ 1208
23.4.7 Interrupt Transfers (PIPE6 and PIPE7)............................................................... 1210
23.4.8 Isochronous Transfers (PIPE1 and PIPE2) ......................................................... 1211
23.4.9 SOF Interpolation Function ................................................................................ 1218
23.4.10 Pipe Schedule...................................................................................................... 1220
23.5 Usage Notes ..................................................................................................................... 1222
23.5.1 Note on Using Isochronous OUT Transfer ......................................................... 1222
23.5.2 Procedure for Setting the USB Transceiver ........................................................ 1223
23.5.3 Timing for the Clearing of Interrupt Sources...................................................... 1224
Section 24 LCD Controller (LCDC)................................................................1225
24.1 Features............................................................................................................................ 1225
24.2 Input/Output Pins ............................................................................................................. 1227
24.3 Register Configuration..................................................................................................... 1228
24.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1229
24.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1231
24.3.3 LCDC Data Format Register (LDDFR) .............................................................. 1234
24.3.4 LCDC Scan Mode Register (LDSMR) ............................................................... 1236
24.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ......... 1238
24.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ......... 1239
24.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ......... 1240
24.3.8 LCDC Palette Control Register (LDPALCR)..................................................... 1241
24.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ..................................... 1242
24.3.10 LCDC Horizontal Character Number Register (LDHCNR) ............................... 1243
24.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR) ....................................... 1244
24.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ........................... 1245
24.3.13 LCDC Vertical Total Line Number Register (LDVTLNR)................................ 1246
24.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ........................................... 1247
24.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ..... 1248
24.3.16 LCDC Interrupt Control Register (LDINTR) ..................................................... 1249
24.3.17 LCDC Power Management Mode Register (LDPMMR).................................... 1252
24.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR) .............................. 1254
24.3.19 LCDC Control Register (LDCNTR)................................................................... 1256
24.3.20 LCDC User Specified Interrupt Control Register (LDUINTR) .......................... 1257
24.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ........... 1259
24.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) ........................ 1260
24.4 Operation ......................................................................................................................... 1261
Rev. 2.00 Apr. 16, 2008 Page xxv of xxx
REJ09B0313-0200