SH7203 Datasheet, PDF (1127/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.3.2 System Configuration Status Register (SYSSTS)
SYSSTS is a register that monitors the line status (D+ and D− lines) of the USB data bus.
This register is initialized by a power-on reset, a software reset, or a USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
- SOFEN -
-
-
LNST[1:0]
Initial value: 0
0
0
0
0
1
0
0
0
0
0
0
0
0
*
*
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
15 to 11 ⎯
10
⎯
9 to 6 ⎯
5
SOFEN
4 to 2 ⎯
Initial
Value R/W Description
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
R
Reserved
The read value is undefined. This bit cannot be
modified.
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R
SOF Issuance Enable
Indicates whether SOF issuance by this module
internal circuit is enabled or disabled, after the UACT
bit in DVSTCTR is written to by software in host
mode operation.
0: SOF issuance to the USB port is disabled.
1: SOF issuance to the USB port is enabled.
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1097 of 1652
REJ09B0313-0200