SH7203 Datasheet, PDF (427/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
22
TL
0
R/W Transfer End Level
Specifies the TEND signal output is high active or low
active. This bit is valid only in CHCR_0 and CHCR_1.
This bit is reserved in CHCR_2 to CHCR_7; it is
always read as 0 and the write value should always be
0.
0: Low-active output from TEND
1: High-active output from TEND
21
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
20
TEMASK 0
R/W TE Set Mask
Specifies that DMA transfer does not stop even if the
TE bit is set to 1. If this bit is set to 1 along with the bit
for SAR/DAR reload function, DMA transfer can be
performed until the transfer request is cancelled.
In auto request mode or when a rising/falling edge of
the DREQ signal is detected in external request mode,
the setting of this bit is ignored and DMA transfer stops
if the TE bit is set to 1.
Note that this function is enabled only when either the
RLDSAR bit or the RLDDAR bit is set to 1.
0: DMA transfer stops if the TE bit is set
1: DMA transfer does not stop even if the TE bit is set
Rev. 2.00 Apr. 16, 2008 Page 397 of 1652
REJ09B0313-0200