SH7203 Datasheet, PDF (806/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
• Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode)
Figure 15.18 shows a sample flowchart for transmitting and receiving serial data
simultaneously.
Use the following procedure for the simultaneous transmission/reception of serial data, after
enabling the SCIF for transmission/reception.
Initialization
Start of transmission and reception
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data to SCFTDR,
read TDFE and TEND flags
in SCFSR as 1,
[1]
and then clear the flags to 0
Read ORER flag in SCLSR
ORER = 1?
No
Read RDF flag in SCFSR
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
flag in SCFSR to 0
No
All data received?
Yes
[2]
Error handling
[3]
[1] SCIF status check and transmit data
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR. Clear the
TDFE and TEND flags to 0 after
reading them as 1. The transition of
the TDFE flag from 0 to 1 can also be
identified by a transmit FIFO data
empty interrupt (TXI).
[2] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0. Reception cannot
be resumed while the ORER flag is
set to 1.
[3] SCIF status check and receive data
read:
Read SCFSR and check that RDF
flag = 1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
0 to 1 can also be identified by a
receive FIFO data full interrupt
(RXI).
[4] Serial transmission and reception
continuation procedure:
To continue serial transmission and
reception, read 1 from the RDF flag
and the receive data in SCFRDR, and
clear the RDF flag to 0 before
receiving the MSB in the current
frame. Similarly, read 1 from the
TDFE flag to confirm that writing is
possible before transmitting the MSB
in the current frame. Then write data
to SCFTDR and clear the TDFE flag
to 0.
Yes
Clear TE and RE bits
in SCSCR to 0
[4]
End of transmission and reception
Note: When switching from a transmit operation
or receive operation to simultaneous
transmission and reception operations,
clear the TE and RE bits to 0, and then
set them simultaneously to 1.
Figure 15.18 Sample Flowchart for Transmitting/Receiving Serial Data
Rev. 2.00 Apr. 16, 2008 Page 776 of 1652
REJ09B0313-0200