SH7203 Datasheet, PDF (928/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 Serial Sound Interface (SSI)
(2) Transmission Using Interrupt Data Flow Control
Start
Release from reset,
set SSICR configuration bits.
Enable SSI module,
enable data interrupts,
enable error interrupts.
For n = ( (CHNL + 1) x 2) Loop
Define TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
DIEN = 1,
UIEN = 1, OIEN = 1
Wait for interrupt from SSI.
Data interrupt?
No
Yes
Load data of channel n
Next channel
Use SSI status register bits
to realign data
after underflow/overflow.
Yes
More data to be send?
No
Disable SSI module,
disable data interrupts
disable error interrupts,
enable Idle interrupt.
EN = 0,
DIEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for Idle interrupt
from SSI module.
End
Figure 18.21 Transmission Using Interrupt Data Flow Control
Rev. 2.00 Apr. 16, 2008 Page 898 of 1652
REJ09B0313-0200