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SH7203 Datasheet, PDF (1633/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series
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Appendix
Pin Function
Type
Pin Name
I/O port PA7 to PA0
PB12
PB11 to PB8
PB7 to PB0
PC14 to PC2, PC0
PC1
PD15 to PD0
PE15 to PE0
H-UDI
PF30 to PF0
TRST
TCK
TDI
TDO
TMS
Emulator*15 AUDSYNC
AUDCK
AUDATA3 to AUDATA0
ASEBRKAK/ASEBRK
Pin State
Normal
Reset State Power-Down State
State (Other Power-
Deep Software Bus
than States On
Pin State Standby Standby Mastership
at Right)
Reset*1 Retained*2 Mode*3 Mode Release
I
Z
Z
Z
Z
I
O
⎯
O/Z*7
O/Z*7 O/Z*7
O
I/O
Z
K/Z*7
K/Z*7 K/Z*7
I/O
I
I
I
I
I
I
I/O
Z
K/Z*7
K/Z*7 K/Z*7
I/O
I/O
Z*5
K/Z*7
K/Z*7 K/Z*7
I/O
I/O
Z*5
K/Z*7
K/Z*7 K/Z*7
I/O
I/O
Z
K/Z*7
K/Z*7 K/Z*7
I/O
I/O
Z
K/Z*7
K/Z*7 K/Z*7
I/O
I
I
I
Z
I
I
I
I
I
Z
I
I
I
I
I
Z
I
I
O/Z*14
O/Z*14 O/Z*14
O/Z*14 O/Z*14
O/Z*14
I
I
I
Z
I
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Z
Z
Z
Z
Z
Z
[Legend]
I:
Input
O: Output
H: High-level output
L:
Low-level output
Z:
High-impedance
K:
Input pins become high-impedance, and output pins retain their state.
Notes: 1. Indicates the power-on reset by low-level input to the RES pin. The pin states after a
power-on reset by the H-UDI reset assert command or WDT overflow are the same as
the initial pin states at normal operation (see section 25, Pin Function Controller (PFC)).
Rev. 2.00 Apr. 16, 2008 Page 1603 of 1652
REJ09B0313-0200
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